Which power-delay-product (pdp) has been calculated all the above circuits are implemented using 180nm cmos technology using a supply voltage of 18v tanner eda environment is used for design and simulation of these circuits keywords cmos comparator, tiq comparator, low power, differential comparator. Adc, comparators influence the overall performance of adc directly this thesis describes a high speed, low offset and low power dissipation preamplifier-latch comparator very useful for pipeline adc design the preamplifier latch comparator, which combine of an amplifier and a latch comparator can obtain high speed. Katyal, vipul, low power high speed and high accuracy design methodologies for pipeline analog-to-digital converters (2008) retrospective i would like to dedicate this thesis to my father, dr o p katyal, an inspiring teacher of physics, to my a new high precision low offset dynamic comparator. Master thesis (2007)  liu haitao, meng qiao, wang zhigonga 2-gsps 6-bit flash analog-to-digital converter in 018-um cmos process high technology, 20 (2) (2010), pp 180-184  tang kai, meng qiao, liu haitao06um cmos 300mhz high-speed voltage comparator design for high-speed adc chinese. A fully differential dynamic latch comparator based on cross-coupled differential pairs is shown in figure 6, which is based on the design of “lewis-gray” dynamic comparator  figure 6 postlayout monte-carlo simulation result with process and.
“i, anand mohan, declare that the phd thesis entitled “reconfigurable analog to digital converter architecture for ultra wideband devices” is no more than 100,000 words in length, exclusive of tables, figures, appendices, references and footnotes this thesis contains no material that has been submitted previously. This thesis demonstrates the process of creating a radiation hardened and extreme temperature operating comparator from start to finish in the 90 nm sige 9hp process node this includes the entire design flow from examining comparator topologies, to designing the initial comparator circuits, to simulating the comparator. The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled cmos technologies the reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced.
Data converters for high speed cmos links a phd thesis submitted to the department of electrical engineering and the committee on graduate studies stanford the resulting large mismatch errors are corrected by small dacs in each comparator the remainder of the chapter presents the circuit design. Analog integrated circuit design 6 cmos comparators 2 sensitivity is the minimum input voltage that produces a consistent output the output peak-to- peak swing is in the range of 3-5 v therefore, for low speed, in order to detect a 1 mv signal a voltage gain of 5000 is required input offset is the voltage that must be. Increasing demand of a high speed comparator for adc, dac and various other in comparator design, such as offset voltage, speed, power and area for following table-i and table-ii shows the comparative analysis of the different architectures of the cmos comparator design which is presented in this thesis.
Meena aggarwal, rajesh mehracomparator design analysis using efficient low power full adder, international journal of engineering trends and technology (ijett), v26(1),50-54 august 2015 issn:2231-5381 www ijettjournalorg published by seventh sense research group abstract in today's electronic industry,. Are use throughout the thesis the different noise analysis techniques are demon - strated with a series of examples chapter 4 discusses the design of efficient low-noise threshold detection compara- tors design equations are presented for a low noise preamplifier for threshold de- tection comparators. 16-bit digital adder design in 250nm and 64-bit digital comparator design in 90nm cmos technologies a thesis submitted in partial fulfillment of the requirements for the degree of master of science in engineering by nv vijaya krishna boppana be, andhra university, 2011 2014 wright state.
This thesis presents synthesis of the reversible comparator the proposed circuits are designed using only parity preserving fredkin and feynman double gates thus, these circuits inherently turn into fault tolerant circuits in addition, a lower bound on the number of constant inputs and garbage outputs for the reversible. This thesis presents a high gain, low noise and low power dynamic residue am- plifier and a low power, low preamp dynamic comparator (plpdc) shows a delay of 250psec for a differential input of 16 pv and and presents a pseudo- latch based dynamic comparator and its design method- ology.